NovaCustom NV4x ADL (Maximized)

Table of contents

1. NovaCustom NV4x ADL (Maximized)
   1. ✅ Active: CPU generation still receiving microcode updates (12th Gen Alder Lake-P)
   2. 🛡️ INCONCLUSIVE (unconfirmed): TPM GPIO Reset
   3. ⚡ Safety First
   4. Disassembly
   5. Flashing

✅ Active: CPU generation still receiving microcode updates (12th Gen Alder Lake-P)

Still receiving microcode updates. See BOARDS_AND_TESTERS.md, Heads threat model.

🛡️ INCONCLUSIVE (unconfirmed): TPM GPIO Reset

GPIO lock absent (Dasharo), mode bits hardware-locked; PLTRST# assertion not confirmed on this PCH die per NV4x ADL-P testing. See Per-Board Protection Status, TPM GPIO Reset Vulnerability.

⚡ Safety First

Before starting, please read our SPI Programmer Best Practices guide for essential safety information and programmer recommendations.

Disassembly

Full disassembly photos, SPI chip details (Macronix MX25L25673GZ4I-08G, 32MB WSON-8, 3.3V), programmer setup, and step-by-step flashing instructions are maintained by Dasharo:

→ Recovery & disassembly photos → Initial deployment (two-step flash) → Hardware matrix

Flashing

Key notes: Intel Boot Guard enabled — external flashing mandatory. Two-step flash (IFD first, then ME+BIOS). Full binaries required. CH341a with WSON-8 probe.